1. Field of the Invention
The present invention relates to a semiconductor device, and more especially, to a method for fabricating shallow trench isolation.
2. Description of the Prior Art
In the integrated circuit industry today, we usually build hundreds of thousands of semiconductor devices on a single chip. Every device on the chip must be electrically isolated to ensure that they operate independently without interfering with each other. The art of isolating semiconductor devices then becomes one important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power. Improper isolation also can exacerbate latch-up, which can damage the circuit temporarily or permanently. In addition, improper isolation can result in noise margin degradation, voltage shift and crosstalk.
Local oxidation of silicon (LOCOS) is one of the most well known techniques for isolation. LOCOS provides the isolation by oxidizing the silicon substrate to create silicon dioxide regions among active devices or functional regions. Because it is easy for the silicon substrate to be oxidized into silicon dioxide, LOCOS has the benefits of its process simplicity and low cost, and it becomes the most widely used isolation technique in very large scale integrated (VLSI) circuit. However, with the tendency for the manufacture of semiconductor integral circuit to high package density, LOCOS meets the limitation in its scalability.
The trench isolation, or, named the shallow trench isolation (STI), is another isolation technique developed especially for semiconductor chip with high integration. The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions. In general, trench isolation has a better scalability in comparison with LOCOS isolation.
In the paper "Characteristics of CMOS Device Isolation for the ULSI Age" in IEDM Tech. Dig., p. 671, 1994, by A. Bryant, et al., the two different isolation techniques of LOCOS and STI are investigated. The writers review how LOCOS and STI isolations are being improved to meet the scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity. For deep sub-micron CMOS generation, the conventional LOCOS isolation suffers from several drawbacks such as large lateral extend of bird's beak, non-planarity, local field oxide thinning effect, and stress-induced silicon defects. The key challenges to LOCOS scaling are insulator thinning at narrow dimension, bird's beak formation, and field-implant encroachment. For future CMOS technology, an effective device isolation method that provides abrupt transitions to active device regions with minimum impact on device characteristics or topography will be required. They come to the conclusions that, at the cost of a trench-fill and planarization, STI is a more direct method of meeting these requirements while benefiting from a significant advantage in planarity.
Another support to STI is given by A. H. Perera, et al., in "TRENCH ISOLATION for 0.45 .mu.m ACTIVE PITCH and BELOW" in IEDM Tech. Dig., p. 679, 1995. They state that developing trench isolation appears expedient for technologies at and below the 0.25 .mu.m size scale, due to the predictable scalability of the technique. And, while trench technology is more complex than simple LOCOS isolation, it is of comparable complexity to advanced LOCOS techniques.
Trench isolation develops to be a better isolation technique in deep sub-micron CMOS generation due to the advantages in its scalability, planarity, and isolation depth. But it still encounters several problems such as silicon damage induced by etching and the corner effects. As mentioned by J. A. Mandelman, et al., in the U.S. pat. No. 5,521,422 entitled "CORNER PROTECTED SHALLOW TRENCH ISOLATION DEVICE", the parasitic leakage path results from an enhancement of the gate electric field near the trench corner. Even worse, the gate conductor could wrap around the trench corner. They propose for above situation a trench isolation structure with a sidewall around. With this sidewall trench structure, the corner parasitic leakage and the gate wrap-around could be solved.